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                            SCHEMA'S




#PAGE 64

TS MODULE HIERARCHIE
See page 31

#IMG book64.jpg

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[[   Afbeeldingen van overige schema's zijn niet beschikbaar   ]]


ORDINATOR            (c) By ORDGROUP
VIDEO CONTROLLER version I
BLOCK DIAGRAM

DESIGN: J. VANDERHOEK


ORDINATOR            (c) By ORDGROUP
VIDEO CONTROLLER version I
Timing unit

DESIGN: GJ DE GROOT


ORDINATOR            (c) By ORDGROUP
VIDEO CONTROLLER version I
Select- and Wait-cycle- generators

DESIGN: GJ DE GROOT


ORDINATOR            (c) By ORDGROUP
VIDEO CONTROLLER version I
6845-CRTC interface

DESIGN: GJ DE GROOT


ORDINATOR            (c) By ORDGROUP
VIDEO CONTROLLER version I
Address- and selectmultipliers

DESIGN: GJ DE GROOT


ORDINATOR            (c) By ORDGROUP
VIDEO CONTROLLER version I
RAM-buffering

DESIGN: GJ DE GROOT


ORDINATOR            (c) By ORDGROUP
VIDEO CONTROLLER version I
Character RAM

DESIGN: GJ DE GROOT


ORDINATOR            (c) By ORDGROUP
VIDEO CONTROLLER version I
Mode-RAM and delay-latches

DESIGN: GJ DE GROOT


ORDINATOR            (c) By ORDGROUP
VIDEO CONTROLLER version I
From ASCII to video

DESIGN: GJ DE GROOT


ORDINATOR            (c) By ORDGROUP
VIDEO CONTROLLER version I
Control bit logic

DESIGN: GJ DE GROOT


ORDINATOR            (c) By ORDGROUP
EPROM PROGRAMMER version I
BLOCK DIAGRAM

DESIGN: J VANDERHOEK


ORDINATOR            (c) By ORDGROUP
EPROM PROGRAMMER version I
BUS INTERFACE/DECODERS

DESIGN: GJ DE GROOT


ORDINATOR            (c) By ORDGROUP
EPROM PROGRAMMER version I
PROGRAMMING-VOLTAGE CONTROLLER

DESIGN: GJ DE GROOT


ORDINATOR            (c) By ORDGROUP
EPROM PROGRAMMER version I
PORT 0FEH / DATABUS BUFFERING

DESIGN: GJ DE GROOT


ORDINATOR            (c) By ORDGROUP
EPROM PROGRAMMER version I
ADDRESSLATCHES / EPROM SOCKETS

DESIGN: GJ DE GROOT


ORDINATOR CPU VII


ORDINATOR CPU IX